Anti-Tamper Digital Clocks - An Overview
Anti-Tamper Digital Clocks - An Overview
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Consequently, the current invention will not be meant to be restricted to the embodiments proven herein but will be to be accorded the widest scope per the ideas and novel capabilities disclosed herein.
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Yet another element of the invention could reside within an equipment for detecting clock tampering, comprising a circuit that provides a monotone sign, a plurality of resettable delay line segments, and an Consider circuit. The circuit provides the monotone signal during a clock Assess time period linked to a clock. The plurality of resettable delay line segments delay the monotone signal to deliver a respective plurality of delayed monotone indicators.
33. The equipment for detecting voltage tampering as outlined in assert 30, whereby the means for evaluating decides irrespective of whether the number of kinds inside the plurality of delayed monotone indicators differs from a water level variety by over a predetermined threshold.
26. The strategy for detecting voltage tampering as defined in declare 23, wherein the evaluate circuit determines whether the volume of types inside the plurality of delayed monotone alerts differs from a water level selection by over a predetermined threshold.
An facet of the present invention could reside in a way for detecting voltage tampering. In the tactic, a plurality of resettable hold off line segments are presented. Resettable hold off line segments among a resettable hold off line section linked to a minimum amount delay time along with a resettable hold off line segment connected with a most delay time are Each and every affiliated with discretely rising delay situations.
Precisely what is claimed is: one. A technique for detecting clock tampering, comprising: supplying a plurality of resettable hold off line segments, whereby resettable hold off line segments between a resettable delay line phase connected with a minimum amount hold off time and also a resettable hold off line segment connected to a utmost hold off time are Each individual related to discretely rising delay situations;
a plurality of resettable delay line segments that hold off the monotone sign to produce a respective plurality of delayed monotone signals Each individual owning either a just one or possibly a zero logic check here value, wherein resettable hold off line segments concerning a resettable delay line section related to a minimum amount delay time plus a resettable hold off line segment associated with a maximum hold off time are each connected to discretely raising hold off situations; and
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In more detailed elements of the creation, the tactic could more incorporate resetting the resettable hold off line segments in the course of a reset time frame.
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